library verilog;
use verilog.vl_types.all;
entity ctrl is
    port(
        instruction     : in     vl_logic_vector(31 downto 0);
        RegDst          : out    vl_logic;
        RegWr           : out    vl_logic;
        ExtOp           : out    vl_logic_vector(1 downto 0);
        nPC_sel         : out    vl_logic_vector(1 downto 0);
        ALUctr          : out    vl_logic_vector(1 downto 0);
        MemtoReg        : out    vl_logic;
        MemWr           : out    vl_logic;
        ALUSrc          : out    vl_logic;
        j_sel           : out    vl_logic;
        rst             : in     vl_logic
    );
end ctrl;
